Low noise tri-state output buffer

ABSTRACT

A buffer circuit includes a pair of pull-up output transistors and a pair of pull-down output transistors driving an output line. Each output transistor is driven by its own tristate input translator, all connected to an input terminal of the circuit. Two of the translators are tristated by control signals received as feedback from the output line to turn off one of the pull-up transistors when the output exceeds the high logic level transition voltage (2.2 V) and to turn off one of the pull-down transistors when the output drops below the low logic level transition voltage (0.8 V). This not only prevents ground bounce or overshoot of the output, but also avoids larger current flow or power dissipation from pull-up and pull-down transistors being simultaneously partially on during a transition. Because the output transistors are driven directly by the input translators, throughput speed is improved, while ramp rate of the translator outputs driving the output transistors can remain slow to reject input noise spikes and avoid generation of output noise.

TECHNICAL FIELD

The present invention relates to electronic digital logic circuitry forinterfacing, i.e. buffering logic signals, between different circuitelements, for example between on-chip circuitry and conductive traces ona printed circuit board leading to other integrated circuit chips. Theinvention particularly relates to buffer circuits with input noiserejection and output switching noise reduction.

BACKGROUND ART

Conventional buffer circuits include a single input translator, i.e.level shifter, that receives an input signal with TTL logic levels (0 Vis low, 3.0 V is high) and that translates that signal to CMOS logiclevels (0 V is low, 5.0 V is high). In both cases the nominal transitionpoint is 1.5 V. This translated signal is then reinverted through a CMOSinverter, since the translator usually has an inverting as well astranslating function, and then goes through a set of logic gates. Thelogic gates include a disable input so that a high impedance state canbe asserted if desired. The set of logic gates then drives pull-up andpull-down output transistors connected to an output line. One problemwith such buffer circuits is that of noise generation. While the inputsignal has a relatively slow ramp rate (3 V/2.5 ns), by the time thesignal has made successive transitions in the translator, inverter andlogic gates, the ramp rate is approximately 8 times higher (5 V/0.5 ns).This causes the output transistors to open and close quickly, whichproduces ground bounce or overshoot of the output signal due to theinductance between the integrated circuit chip's internal ground andpower supply and external ground and power supply. The buffer circuitalso has a relatively slow throughput time due to the many layers oflogic between the input and output of the circuit. An ideal buffer wouldbe relatively fast and yet would linearly ramp its output current to amaximum to reduce ground bounce or overshoot and then linearly ramp downits output current to source small DC current sufficient to maintain thefinal voltage on the output line. It would also reject input noisespikes instead of transmitting them to the output.

In U.S. Pat. No. 5,381,059, Douglas describes a tristate buffer circuitwith parallel pairs of pull-up and pull-down transistors that are drivenby separate control signals. A feedback circuit coupled between theoutput node and the pull-up transistors prevents leakage current fromflowing in the buffer. Like conventional circuits, there is considerablelogic between the data input terminal and the transistors in the outputstage.

In U.S. Pat. No. 5,355,029, Houghton et al. describe a circuit withparallel drivers, each with their own predriver stage. Like conventionalbuffers, the predriver stages consist of transistors forming AND and NORgates connected to the output of a single input transistor.

In U.S. Pat. No. 4,806,794, Walters, Jr. describes a buffer circuit withan output stage having dynamic pull-up and pull-down circuit elementsthat drive the output transistors and a keeper circuit element. Thekeeper maintains the output node at the high or low logic level after ithas completed a low-to-high or high-to-low transition. In this case,"after" is defined with respect to a delay generated by the circuitry.Since the delay is a function of the load that the current is driving,proper operation depends to some extent on the load being known. Forexample, a buffer circuit of this type with a 4.2 nsec propagation timewhen driving a 50 pF load would have a 10.2 nsec propagation time whendriving a 250 pF load. It is desirable in buffer circuits to have thepropagation time generally independent of the load, since the load isusually not known in advance.

An object of the present invention is to provide a buffer circuit whichis faster, rejects input noise spikes and does not generate noise at theoutput, and which has low power dissipation.

DISCLOSURE OF THE INVENTION

The above object has been met with a low noise fast buffer circuithaving dual tristate input translators in parallel driving a pull-uptransistor and a pull-down transistor, respectively with means forshutting off these pull-up and pull-down transistors when the inputtranslators are tristated. (Tristate input translators, inverters andbuffers have both high and low output states and also a third highimpedance state. These circuit elements are said to be "tristated", i.e.placed in their high impedance state, by a separate control signalinput.) Further, the circuit includes a parallel set of pull-up andpull-down transistors that also receive tristatable inputs throughanother pair of input translators. Feedback means shut off at least oneof the pull-up transistors during a low-to-high transition after a logichigh transition voltage has been reached at the output, and similarlyshut off at least one of the pull-down transistors during a high-to-lowtransition after a logic low transition voltage has been reached at theoutput. This prevents overshoot or undershoot of the output.

The circuit filters out unwanted input noise spikes, because the inputtranslators drive the pull-up and pull-down transistors with arelatively slow ramp rate, so that spikes of less than 1 nsec durationand less than 1.8 V peaks do not turn the transistors on sufficiently topull the output through the transition point. The buffer circuit is alsofast, because the input translators drive the pull-up and pull-downtransistors directly, rather than through several stages of logic gates.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic circuit diagram of a buffer circuit of the presentinvention.

FIG. 2 is a schematic transistor level diagram of an input translatorcircuit element used in the buffer circuit of FIG. 1.

FIG. 3 is a schematic transistor level diagram of a NOR gate used in thefeedback portion of the buffer circuit of FIG. 1.

BEST MODE OF CARRYING OUT THE INVENTION

With reference to FIG. 1, a buffer circuit of the present inventionincludes a first pull-up transistor 11, a second pull-up transistor 13,a first pull-down transistor 15, and a second pull-down transistor 17.All four of these transistors are field-effect transistors connected toan output line 19 to form the output transistors that drive an outputterminal 20 of the circuit. The pull-up transistors 11 and 13 are alsoconnected to a first voltage supply line V_(dd), while the pull-downtransistors 15 and 17 are connected to a second voltage supply lineV_(ss). Typically, the second voltage line V_(ss) is defined as being atthe reference or ground voltage (0 V), while the first voltage lineV_(dd) is at +5 V. The two pull-down transistors 15 and 17 are n-channeldevices, while the second pull-up transistor 13 is a p-channel device.In buffer circuits that operate with TTL input/output logic levels (LOW<0.8 V , HIGH >2.0 V), the first pull-up transistor 11 is preferably ann-channel device with a CMOS inverter 21 between the input stage of thecircuit and the control gate of transistor 11. The use of an n-channeldevice for pull-up transistor 11 minimizes power dissipation for reasonsthat will be discussed below. Alternatively, if the buffer circuit is tooperate with pure CMOS output levels, a p-channel device will substitutefor the n-channel pull-up transistor 11 of FIG. 1 and the inverter 21will be removed. This will enable the output terminal 20 to be pulledall the way up to V_(DD) =5 V without the 1 to 1.5 V threshold voltagedrop of an n-channel device.

The input terminal 22 of the buffer circuit connects in parallel to fourtristate inverting input translators 23, 25, 27 and 29, with a separatetranslator being provided for driving each one of the four outputtransistors 11, 13, 15 and 17 respectively. Pull-up transistors 31 and33 are connected at nodes 32 and 34 between the outputs of inputtranslators 23 and 25 and the inputs of output transistors 11 and 13. Inthe case of n-channel pull-up transistor 11, the node 32 communicatesonly indirectly with the gate of transistor 11 via inverter 21.Pull-down transistors 35 and 37 are connected at nodes 36 and 38 betweenthe outputs of input translators 27 and 29 and the inputs of outputtransistors 15 and 17. Transistors 31 and 33 are p-channel devicesconnected to first voltage supply line V_(dd), while transistors 35 and37 are n-channel devices connected to second voltage supply line V_(ss).Transistors 31, 33, 35 and 37 are driven by control signals OE, S1, OE,and S2 applied to their gates that cause their corresponding outputtransistors 11, 13, 15 and 17 to turn off when the input translators 23,25, 27 and 29 are placed in a high impedance state by related controlsignals OE, S1, OE and S2.

There are no logic gates, other than the first CMOS inverter 21, betweenthe input translators 23, 25, 27 and 29 and the output transistors 11,13, 15 and 17. Rather, the input translators drive the outputtransistors directly. In contrast, in conventional buffer circuits,input signals generally traverse several levels of logic, including NANDor NOR gates, before reaching the output transistors. Time is saved bynot going through these extra levels of logic. Thus, this structureleads to a fast buffer.

The input translators 23, 25, 27 and 29 are typically sized to all havea 1.5 V transition voltage, which is the nominal transition voltage forTTL logic. Alternatively, the input translators 23 and 25 that drive thepull-up output transistors 11 and 13 may be sized to have a smallertransition point somewhere between 0.8 V and 1.5 V, for example, 1.2 V,while the input transistors 27 and 29 that drive the pull-down outputtransistors 15 and 17 may be sized to have a larger transition pointsomewhere between 1.5 V and 2.0 V, for example 1.8 V. This difference ininput thresholds for the translators 23, 25, 27 and 29 hastens thethroughput of a transition of an input signal at the input terminal 22of the circuit, albeit at the expense of some input noise spikerejection, without increasing the ramp rate of the translators' outputsdriving the output transistors 11, 13, 15 and 17. Basically, atransition from low-to-high by the input signal is recognized as atransition by the input translators 23 and 25 sooner because theirtransition point is lower than 1.5 V, and similarly a high-to-lowtransition is recognized sooner by the input translators 27 and 29because their transition point is higher than 1.5 V. Driving of thepull-up or pull-down transistors 11, 13, 15 and 17 is at the same ramprate but occurs sooner after the start of an input signal transition. Inyet another alternative, the translators 23 and 27 driving the weakeroutput transistors 11 and 15, which are mainly used to complete atransition and maintain the output level after the finish of atransition, may have a 1.5 V transition voltage, while only thetranslators 25 and 29 driving the stronger output transistors 13 and 17have different transition voltages as described above.

The circuit minimizes the generation of noise at the output by avoidingground bounce. The input signal received at the input terminal 22normally has a relatively slow ramp rate of about 3 V/2.5 ns. However,in conventional buffers by the time the signal has traversed the logicgates to reach the gates of the output transistors, the ramp rate hasincreased substantially to about 5 V/0.5 ns. This causes the outputtransistors to open and close quickly, leading to a rapid change incurrent flow (dI/dt) and ground bounce proportional to L·dI/dt, where Lis the inductance between the circuit's ground V_(ss) and an externalground. In the circuit of the present invention, the transistors thatmake up the input translators 23, 25, 27 and 29, as seen in FIG. 2, havesizes chosen so that their outputs, which directly drive the gates ofthe output transistors, still have relatively slow ramp rates. Inparticular, around the transition point, the input translators operateas linear inverting amplifiers, where the output has a transition rateproportional to and at most two times higher than that at its input.Signal transitions of about 2.25 V/ns drive the output transistors 13,15 and 17. The transistor 11 is driven by the inverter 21, whose outputramp is also slow because of its small size in relation to the load itdrives. In addition, the relative size of the output transistors to theinput translators is chosen to ensure that the slow transition ismaintained by the output transistors. The slow turn on or turn off ofthe output transistors results in a slow change in current flow (smalldI/dt), thereby minimizing ground bounce. Note that the slowertransition rates are more than compensated for by the shorter throughputtime achieved by the fewer logic levels traversed by the signal.

As seen in FIG. 2, the buffer circuit uses a tristate input translatorthat includes an inverter element 41 with a p-channel pull-up transistor43 and an n-channel pull-down transistor 45, and two n-channeltransistors 47 and 49 connecting the inverter element 41 to therespective first and second voltage supply lines V_(dd) and V_(ss). Thetransistors 47 and 49 both have an enable control signal EN applied totheir gates. The gates of the transistors 43 and 45 of the inverterelement 41 receive an input signal on common input line 51, and providean inverted and translated output signal on a common output line 53whenever the transistors 47 and 49 are turned on (EN=high). The outputline 53 is in a high impedance state when the transistors 47 and 49 areoff (EN=low). The relative strengths or saturation currents of thepull-up and pull-down transistors determine the nominal transitionvoltage as well as the ramp rate of the output. While the transistorsizes (channel widths and lengths) are process dependent, representativesize values for a 1.5 V transition level for TTL input signals and a lowramp rate are 12/0.8 (channel width/channel length in microns) forn-channel transistor 47, 18/0.8 for p-channel transistor 43, and 9/0.8for both n-channel pull-down transistors 45 and 49. The sizes willdiffer for translators with other transition levels. If n-channeltransistor 47 is replaced by a p-channel transistor so as to pull theoutput 53 all the way up to V_(dd) instead of just to 3 V, thattransistor would have the same 18/0.8 size as transistor 43. The CMOSinverter 21 has p-channel and n-channel transistors whose sizes may bothbe 19.5/0.8. Transistor 11 is turned on very slowly due to the weakpull-up of inverter 21.

To maintain the slow transition of the output transistors 11, 13, 15 and17 in FIG. 1 without ground bounce, representative effective sizes usingthe same transistor process are 700/0.8 for n-channel transistor 11,620/0.8 for p-channel transistor 13, 120/0.8 for n-channel transistor 15and 680/0.8 for n-channel transistor 17. Each of these outputtransistors may be formed by a set of parallel transistors all sized atabout 20/0.8. Thus, for example, transistor 11 could be formed by 35 ofsuch parallel transistors.

In addition to avoiding the generation of noise from ground bounce, thebuffer circuit also filters out any unwanted input spikes. This can beunderstood by considering an input transition from low to high. By thetime the input signal has risen to 1.8 V, the outputs of the inputtranslators will have fallen only from 5 V to 3.5 V. While this startsthe opening of at least the pull-up transistor 13 and the closing of thepull-down transistor 15, neither of these transistors is fully open orshut yet, and the output 20 will not have moved through the transitionpoint, i.e. have dropped below 2.0 V. By contrast, conventional bufferswill usually have switched at this point, with their logic outputs fullylow and their p-channel pull-up and n-channel pull-down outputtransistors fully open and shut, respectively. The circuit of thepresent invention will reject a 1 ns wide input noise spike from 0 V to1.8 V (or from 3.0 V to 1.2 V) without producing a corresponding spiketransition at the output. That is, the output will not rise above 0.8 V(the upper limit of a low logic value) or drop below 2.0 V (the lowerlimit of a high logic value) when such 1.8 V spikes are received at theinput 22.

The buffer circuit in FIG. 1 includes a pair of feedback elements 61 and63 responsive to the voltage level on the output terminal 20 forcontrolling the state of two of the output transistors 13 and 17. Thefeedback element 61 includes a NOR gate 65 with one input connected tothe output line 19 and another input connected to receive a disablesignal OE. An inverter 67 with a weak pull-up transistor 69 is connectedto the output of NOR gate 65. The NOR gate has a transition point ofabout 2.2 V. When the output 20 exceeds this transition point, controlsignal S1 on the output of NOR gate 65 is low and control signal S1 onthe output of inverter 67 is high, tristating the input translator 25and shutting off output transistor 13. The feedback element 63 includesan inverter 71 connecting the output line 19 of the buffer circuit to aninput of another NOR gate 73. Another input of the NOR gate 73 receivesa disable signal OE. A second inverter 75 with a weak pull-up transistor77 is connected to the output of the NOR gate 73. The inverter 71 has atransition point of 1.0 V. When the output 20 drops below thistransition point, control signal S2 on the output of the second inverter75 is high, tristating the input translator 29 and shutting off outputtransistor 17. Second pull-down transistor 17 is much larger than firstpull-down transistor 15 (about 6× larger) and is big enough to pull theoutput line 19 down rapidly. Transistor 17 is enabled when the output ishigh, but is then switched off by control signal 52 when the outputfalls below 1.0 V. Transistor 15 is used to complete the pull-down ofthe output at a slow enough rate to avoid undershoot and then to providethe current sink needed to keep the output low. Similarly, secondpull-up transistor 13 is stronger than first pull-up transistor 11 andis used to pull the output line 19 up rapidly until the output exceeds2.2 V. Then control signals S1 and S1 shut the transistor 13 off.Transistor 11 completes the pull-up (to about 3.0 V) and sustains thehigh output level.

This use of two pull-up output transistors and two pull-down outputtransistors of different strengths when one pull-up or pull-downtransistor is turned off after the logic transition level has beenreached also removes the power dissipation that would otherwise bepresent during a transition due to both pull-up and pull-downtransistors being partially on simultaneously. Consider the case whenthe input 22 and output 20 are initially low. Pull-down transistor 15 isconducting to keep the output low, but the second pull-down transistor17 is not conducting, because it has been switched off by control signalS2. As the input signal level rises, transistor 15 gradually shuts off,while pull-up transistors 11 and 13 gradually turn on and begin toconduct. Although a conduction path is opened between V_(dd) and V_(ss),this path has relatively high resistance due to the relatively smallsize of transistor 15 and the fact that the larger pull-down transistor17 remains off. Thus, power dissipation is insignificant. Likewise,during a transition from high to low, pull-up transistor 13 is off dueto control signals S1 and S1. Although transistors 11, 15 and 17 aresimultaneously partially on as transistor 11 gradually shuts off andpull-down transistors 15 and 17 gradually turn on, the relatively highresistance of transistor size keeps current flow to a minimum. With theexemplary output transistor sizes given previously, power consumptionthrough this conductive path is typically less than 10 μA/mHz.

Referring again to FIG. 2, the buffer circuit uses n-channel pull-uptransistors 47 in its translators to reduce leakage current. One problemwith conventional translators that use a p-channel transistor in thatlocation is that they leak current whenever the input level is between 3V and 4 V. Then for V_(dd) =5 V, both p-channel pull-up transistors andboth n-channel pull-down transistors are partially conducting. Thecurrent flow is substantial, since the node between the two pull-updevices is at V_(dd) =5 V while the gate voltage on the device 43 is atV_(in) =3 V and current is proportional to [V_(gate) -V_(source) ]². Inthe translators of the present invention, the use of an n-channelpull-up device 47 causes the node between the pull-up devices 47 and 43to be a threshold drop below V_(dd), i.e. about 4 V, and so leakagecurrent through the p-channel device 43 is about 75% less.

For similar reasons the weak pull-up transistors 95 and 99 off of thesignal lines leading to inverter 21 and p-channel output transistor 13and activated by inverters 93 and 97 respectively ensure that, whenthose lines 32 and 34 go high, they are pulled completely up to V_(dd)=5 V. This will prevent leakage current through the inverter 21'sp-channel device and the p-channel transistor 13, since their gates willbe maintained at V_(dd).

In the overall buffer circuit seen in FIG. 1, the use of an n-channelpull-up device 11 for one of the output transistors reduces powerdissipation as the output line 19 transitions between low (0 V) and high(preferably above 3.4 V). The power needed to cause such transitions ina capacitive circuit is CV² f, where C is the capacitance of thecircuit, V is the voltage change, and f is the frequency. Thecapacitance C is made up of components from the trace on the printedcircuit board to which the chip is connected and that from the pinsconnecting the chip to the trace. Power dissipation is minimized whenthe voltage swing is limited to not more than 3.8 V. In the presentbuffer circuit, recall that p-channel pull-up transistor 13 startspulling the output up and then is switched off by control signals S1 andS1 when the input level rises above about 2.2 V. Then n-channeltransistor 11 completes the pull-up. However, because it is an n-channeldevice, it can only pull it up to a threshold drop below V_(dd), i.e.about 3.8 V. Accordingly, power consumption is minimized by the limitedvoltage swing. Alternatively, if CMOS output levels are desired, ap-channel transistor must be used in place of transistor 11 in order topull the output line 19 all the way up to the power supply voltageV_(dd).

In FIG. 3, a NOR gate 65 with 2.2 V transition voltage includes seriespull-up transistors 81 and 83 and parallel pull-down transistors 85 and87. One pull-up and one pull-down transistor 81 and 85 are connected tothe input 89, while the other transistors 83 and 87 received enablecontrol signals OE and OE for when the buffer is tristated. The pull-uptransistor 83 closest to the power supply line V_(dd) is an n-channeldevice to provide a threshold drop to reduce power consumption byp-channel pull-up transistor 81. Typical process dependent transistorsizes are 22.5/0.8 for transistor 83, 16/0.8 for transistor 81, 25/0.8for transistor 85 ad 8/0.8 for transistor 87.

The buffer circuit of the present invention is thus seen to be fast,have low power consumption, reduced ground bounce or overshoot of theoutput signal, and input noise spike rejection.

I claim:
 1. A buffer circuit, comprisinga first pair of tristate inputtranslators connected in parallel to an input of the circuit, each inputtranslator being characterized by a ramp rate for a signal transitionthat is at most two times higher at its output than at its input, afirst set of pull-up and pull-down output transistors connected inseries between first and second voltage supply lines with an output nodeformed between said pull-up and pull-down output transistorst said inputtranslators driving respective control gates of said pull-up andpull-down output transistors, wherein said input translator that drivessaid pull-up transistor of said first set of output transistors has aninput transition voltage that is lower than a nominal transition voltageof the circuit and said input translator that drives said pull-downtransistor of said first set of output transistors has a different inputtransition voltage that is higher than said nominal transition voltage,said nominal transition voltage being between voltage levels of saidfirst and second voltage supply lines and between predefined logic lowand logic high voltage levels for input signals received at said inputof the circuit, and means connected in parallel with said inputtranslators to said control gates for shutting off said pull-up andpull-down output transistors whenever said input translators are in ahigh impedance state.
 2. The buffer circuit of claim 1 furthercomprisinga second set of pull-up and pull-down output transistorsconnected in series between said first and second voltage supply linesin parallel with said first set of pull-up and pull-down outputtransistors with said output node also connected between said pull-upand pull-down output transistors of said second set, and a second pairof tristate input translators connected in parallel with each other andwith said first pair of tristate input translators to said input of thecircuit, each of said second pair of input translators also beingcharacterized by a ramp rate for a signal transition that is at most twotimes higher at its output than at its input, said second pair oftristate input translators driving respective control gates of saidsecond set of pull-up and pull-down output transistors.
 3. A buffercircuit, comprisinga first pair of tristate input translators connectedin parallel to an input of the circuit, each input translator beingcharacterized by a ramp rate for a signal transition that is at most twotimes higher at its output than at its input, a first set of pull-up andpull-down output. transistors connected in series between first andsecond voltage supply lines with an output node formed between saidpull-up and pull-down output transistors, said input translators drivingrespective control gates of said pull-up and pull-down outputtransistors, wherein said input translator that drives said pull-uptransistor of said first set of output transistors has an inputtransition voltage that is lower than a nominal transition voltage ofthe circuit and said input translator that drives said pull-downtransistor of said first set of output transistors has a different inputtransition voltage that is higher than said nominal transition voltage,said nominal transition voltage being between voltage levels of saidfirst and second voltage supply lines and between predefined logic lowand logic high voltage levels for input signals received at said inputof the circuit, a second set of pull-up and pull-down output transistorsconnected in series between said first and second voltage supply linesin parallel with said first set of pull-up and pull-down outputtransistors with said output node also connected between said pull-upand pull-down output transistors of said second set, a second pair oftristate input translators connected in parallel with each other andwith said first pair of tristate input translators to said input of thecircuit, each of said second pair of input translators also beingcharacterized by a ramp rate for a signal transition that is at most twotimes higher at its output than at its input, said second pair oftristate input translators driving respective control gates of saidsecond set of pull-up and pull-down output transistors, and meansresponsive to a voltage level of said output node and connected to saidcontrol gates of said second set of pull-up and pull-down outputtransistors for shutting off said pull-up transistor of said second setduring a low-to-high transition when said output node has exceeded afirst voltage level and shutting off said pull-down transistor of saidsecond set during a high-to-low transition when said output node hasfallen below a second voltage level, said first and second voltagelevels both being between voltage levels of said first and secondvoltage supply lines.
 4. A buffer circuit, comprisingfirst and secondpull-up output transistors connected in parallel between a first voltagesupply line and an output node, first and second pull-down outputtransistors connected in parallel between a second voltage supply lineand said output node, first, second, third and fourth tristate inputtranslators with inputs connected in common to an input terminal of thecircuit and with outputs respectively driving said first and secondpull-up and first and second pull-down output transistors, and feedbackmeans connected to said output node for generating first and secondcontrol signals when said output node respectively exceeds a logic hightransition voltage and falls below a logic low transition voltage, saidfirst control signal being coupled to a tristate input of said secondinput translator driving said second pull-up output transistor, saidsecond control signal being coupled to a tristate input of said fourthinput translator driving said second pull-down output transistor.
 5. Thecircuit of claim 4 wherein said first pull-up output transistor is ann-channel transistor.
 6. The circuit of claim 4 wherein each inputtranslator comprisesa first n-channel pull-up transistor, a secondp-channel pull-up transistor, a third n-channel pull-down transistor anda fourth n-channel pull-down transistor connected in series between saidfirst and second voltage supply lines, said second and third transistorsconnected at their gates to said input terminal, said first and fourthtransistors connected at their gates to a tristate input of said inputtranslator, a node between said second and third transistors forming anoutput of said input translator.
 7. The circuit of claim 4 wherein saidsecond input translator has a first input transition voltage that isless than a nominal transition voltage of the circuit and said fourthinput translator has a second input transition voltage that is greaterthan said nominal transition voltage of the circuit, said nominaltransition voltage of the circuit being between predefined logic low andlogic high voltage levels for input signals received at said inputterminal.
 8. The circuit of claim 4 wherein said feedback meanscomprisesa first NOR gate with an input connected to said output node,said first NOR gate having a transition voltage substantially equal tosaid logic high transition voltage and providing said first controlsignal at an output thereof, and a second NOR gate with an input coupledto said output node via an inverter, said inverter having a transitionvoltage substantially equal to said logic low transition voltage, saidsecond NOR gate providing said second control signal at an outputthereof.